Name |
Value |
C_PIM4_SUBTYPE |
INACTIVE |
C_XCL4_LINESIZE |
4 |
C_XCL4_WRITEXFER |
1 |
C_XCL4_PIPE_STAGES |
2 |
C_XCL4_B_IN_USE |
0 |
C_PIM4_B_SUBTYPE |
INACTIVE |
C_XCL4_B_LINESIZE |
4 |
C_XCL4_B_WRITEXFER |
1 |
C_SPLB4_AWIDTH |
32 |
C_SPLB4_DWIDTH |
64 |
C_SPLB4_NATIVE_DWIDTH |
64 |
C_SPLB4_NUM_MASTERS |
1 |
C_SPLB4_MID_WIDTH |
1 |
C_SPLB4_P2P |
1 |
C_SPLB4_SUPPORT_BURSTS |
0 |
C_SPLB4_SMALLEST_MASTER |
32 |
C_SDMA_CTRL4_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL4_HIGHADDR |
0x00000000 |
C_SDMA_CTRL4_AWIDTH |
32 |
C_SDMA_CTRL4_DWIDTH |
64 |
C_SDMA_CTRL4_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL4_NUM_MASTERS |
1 |
C_SDMA_CTRL4_MID_WIDTH |
1 |
C_SDMA_CTRL4_P2P |
1 |
C_SDMA_CTRL4_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL4_SMALLEST_MASTER |
32 |
C_SDMA4_COMPLETED_ERR_TX |
1 |
C_SDMA4_COMPLETED_ERR_RX |
1 |
C_SDMA4_PRESCALAR |
1023 |
C_SDMA4_PI2LL_CLK_RATIO |
1 |
C_PPC440MC4_BURST_LENGTH |
4 |
C_PPC440MC4_PIPE_STAGES |
1 |
C_VFBC4_CMD_FIFO_DEPTH |
32 |
C_VFBC4_CMD_AFULL_COUNT |
3 |
C_VFBC4_RDWD_DATA_WIDTH |
32 |
C_VFBC4_RDWD_FIFO_DEPTH |
1024 |
C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT |
3 |
C_PI4_RD_FIFO_TYPE |
BRAM |
C_PI4_WR_FIFO_TYPE |
BRAM |
C_PI4_ADDRACK_PIPELINE |
1 |
C_PI4_RD_FIFO_APP_PIPELINE |
1 |
C_PI4_RD_FIFO_MEM_PIPELINE |
1 |
C_PI4_WR_FIFO_APP_PIPELINE |
1 |
C_PI4_WR_FIFO_MEM_PIPELINE |
1 |
C_PI4_PM_USED |
1 |
C_PI4_PM_DC_CNTR |
1 |
C_PIM5_BASEADDR |
0xFFFFFFFF |
C_PIM5_HIGHADDR |
0x00000000 |
C_PIM5_OFFSET |
0x00000000 |
C_PIM5_DATA_WIDTH |
64 |
C_PIM5_BASETYPE |
0 |
C_PIM5_SUBTYPE |
INACTIVE |
C_XCL5_LINESIZE |
4 |
C_XCL5_WRITEXFER |
1 |
C_XCL5_PIPE_STAGES |
2 |
C_XCL5_B_IN_USE |
0 |
C_PIM5_B_SUBTYPE |
INACTIVE |
C_XCL5_B_LINESIZE |
4 |
C_XCL5_B_WRITEXFER |
1 |
C_SPLB5_AWIDTH |
32 |
C_SPLB5_DWIDTH |
64 |
C_SPLB5_NATIVE_DWIDTH |
64 |
C_SPLB5_NUM_MASTERS |
1 |
C_SPLB5_MID_WIDTH |
1 |
C_SPLB5_P2P |
1 |
C_SPLB5_SUPPORT_BURSTS |
0 |
C_SPLB5_SMALLEST_MASTER |
32 |
C_SDMA_CTRL5_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL5_HIGHADDR |
0x00000000 |
C_SDMA_CTRL5_AWIDTH |
32 |
C_SDMA_CTRL5_DWIDTH |
64 |
C_SDMA_CTRL5_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL5_NUM_MASTERS |
1 |
C_SDMA_CTRL5_MID_WIDTH |
1 |
C_SDMA_CTRL5_P2P |
1 |
C_SDMA_CTRL5_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL5_SMALLEST_MASTER |
32 |
C_SDMA5_COMPLETED_ERR_TX |
1 |
C_SDMA5_COMPLETED_ERR_RX |
1 |
C_SDMA5_PRESCALAR |
1023 |
C_SDMA5_PI2LL_CLK_RATIO |
1 |
C_PPC440MC5_BURST_LENGTH |
4 |
C_PPC440MC5_PIPE_STAGES |
1 |
C_VFBC5_CMD_FIFO_DEPTH |
32 |
C_VFBC5_CMD_AFULL_COUNT |
3 |
C_VFBC5_RDWD_DATA_WIDTH |
32 |
C_VFBC5_RDWD_FIFO_DEPTH |
1024 |
C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT |
3 |
C_PI5_RD_FIFO_TYPE |
BRAM |
C_PI5_WR_FIFO_TYPE |
BRAM |
C_PI5_ADDRACK_PIPELINE |
1 |
C_PI5_RD_FIFO_APP_PIPELINE |
1 |
C_PI5_RD_FIFO_MEM_PIPELINE |
1 |
C_PI5_WR_FIFO_APP_PIPELINE |
1 |
C_PI5_WR_FIFO_MEM_PIPELINE |
1 |
C_PI5_PM_USED |
1 |
C_PI5_PM_DC_CNTR |
1 |
C_PIM6_BASEADDR |
0xFFFFFFFF |
C_PIM6_HIGHADDR |
0x00000000 |
C_PIM6_OFFSET |
0x00000000 |
C_PIM6_DATA_WIDTH |
64 |
C_PIM6_BASETYPE |
0 |
C_PIM6_SUBTYPE |
INACTIVE |
C_XCL6_LINESIZE |
4 |
C_XCL6_WRITEXFER |
1 |
C_XCL6_PIPE_STAGES |
2 |
C_XCL6_B_IN_USE |
0 |
C_PIM6_B_SUBTYPE |
INACTIVE |
C_XCL6_B_LINESIZE |
4 |
C_XCL6_B_WRITEXFER |
1 |
C_SPLB6_AWIDTH |
32 |
C_SPLB6_DWIDTH |
64 |
C_SPLB6_NATIVE_DWIDTH |
64 |
C_SPLB6_NUM_MASTERS |
1 |
C_SPLB6_MID_WIDTH |
1 |
C_SPLB6_P2P |
1 |
C_SPLB6_SUPPORT_BURSTS |
0 |
C_SPLB6_SMALLEST_MASTER |
32 |
C_SDMA_CTRL6_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL6_HIGHADDR |
0x00000000 |
C_SDMA_CTRL6_AWIDTH |
32 |
C_SDMA_CTRL6_DWIDTH |
64 |
C_SDMA_CTRL6_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL6_NUM_MASTERS |
1 |
C_SDMA_CTRL6_MID_WIDTH |
1 |
C_SDMA_CTRL6_P2P |
1 |
C_SDMA_CTRL6_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL6_SMALLEST_MASTER |
32 |
C_SDMA6_COMPLETED_ERR_TX |
1 |
C_SDMA6_COMPLETED_ERR_RX |
1 |
C_SDMA6_PRESCALAR |
1023 |
C_SDMA6_PI2LL_CLK_RATIO |
1 |
C_PPC440MC6_BURST_LENGTH |
4 |
C_PPC440MC6_PIPE_STAGES |
1 |
C_VFBC6_CMD_FIFO_DEPTH |
32 |
C_VFBC6_CMD_AFULL_COUNT |
3 |
C_VFBC6_RDWD_DATA_WIDTH |
32 |
C_VFBC6_RDWD_FIFO_DEPTH |
1024 |
C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT |
3 |
C_PI6_RD_FIFO_TYPE |
BRAM |
C_PI6_WR_FIFO_TYPE |
BRAM |
C_PI6_ADDRACK_PIPELINE |
1 |
C_PI6_RD_FIFO_APP_PIPELINE |
1 |
C_PI6_RD_FIFO_MEM_PIPELINE |
1 |
C_PI6_WR_FIFO_APP_PIPELINE |
1 |
C_PI6_WR_FIFO_MEM_PIPELINE |
1 |
C_PI6_PM_USED |
1 |
C_PI6_PM_DC_CNTR |
1 |
C_PIM7_BASEADDR |
0xFFFFFFFF |
C_PIM7_HIGHADDR |
0x00000000 |
C_PIM7_OFFSET |
0x00000000 |
C_PIM7_DATA_WIDTH |
64 |
C_PIM7_BASETYPE |
0 |
C_PIM7_SUBTYPE |
INACTIVE |
C_XCL7_LINESIZE |
4 |
C_XCL7_WRITEXFER |
1 |
C_XCL7_PIPE_STAGES |
2 |
C_XCL7_B_IN_USE |
0 |
C_PIM7_B_SUBTYPE |
INACTIVE |
C_XCL7_B_LINESIZE |
4 |
C_XCL7_B_WRITEXFER |
1 |
C_SPLB7_AWIDTH |
32 |
C_SPLB7_DWIDTH |
64 |
C_SPLB7_NATIVE_DWIDTH |
64 |
C_SPLB7_NUM_MASTERS |
1 |
C_SPLB7_MID_WIDTH |
1 |
C_SPLB7_P2P |
1 |
C_SPLB7_SUPPORT_BURSTS |
0 |
C_SPLB7_SMALLEST_MASTER |
32 |
C_SDMA_CTRL7_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL7_HIGHADDR |
0x00000000 |
C_SDMA_CTRL7_AWIDTH |
32 |
C_SDMA_CTRL7_DWIDTH |
64 |
C_SDMA_CTRL7_NATIVE_DWIDTH |
32 |
C_SDMA_CTRL7_NUM_MASTERS |
1 |
C_SDMA_CTRL7_MID_WIDTH |
1 |
C_SDMA_CTRL7_P2P |
1 |
C_SDMA_CTRL7_SUPPORT_BURSTS |
0 |
C_SDMA_CTRL7_SMALLEST_MASTER |
32 |
C_SDMA7_COMPLETED_ERR_TX |
1 |
C_SDMA7_COMPLETED_ERR_RX |
1 |
C_SDMA7_PRESCALAR |
1023 |
C_SDMA7_PI2LL_CLK_RATIO |
1 |
C_PPC440MC7_BURST_LENGTH |
4 |
C_PPC440MC7_PIPE_STAGES |
1 |
C_VFBC7_CMD_FIFO_DEPTH |
32 |
C_VFBC7_CMD_AFULL_COUNT |
3 |
C_VFBC7_RDWD_DATA_WIDTH |
32 |
C_VFBC7_RDWD_FIFO_DEPTH |
1024 |
C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT |
3 |
C_PI7_RD_FIFO_TYPE |
BRAM |
C_PI7_WR_FIFO_TYPE |
BRAM |
C_PI7_ADDRACK_PIPELINE |
1 |
C_PI7_RD_FIFO_APP_PIPELINE |
1 |
C_PI7_RD_FIFO_MEM_PIPELINE |
1 |
C_PI7_WR_FIFO_APP_PIPELINE |
1 |
C_PI7_WR_FIFO_MEM_PIPELINE |
1 |
C_PI7_PM_USED |
1 |
C_PI7_PM_DC_CNTR |
1 |
C_WR_TRAINING_PORT |
0 |
C_ARB_BRAM_INIT_00 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000 |
C_ARB_BRAM_INIT_01 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_BRAM_INIT_02 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000 |
C_ARB_BRAM_INIT_03 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_BRAM_INIT_04 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000 |
C_ARB_BRAM_INIT_05 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_BRAM_INIT_06 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000 |
C_ARB_BRAM_INIT_07 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_NCK_PER_CLK |
1 |
C_TWR |
0 |
C_CTRL_COMPLETE_INDEX |
0 |
C_CTRL_IS_WRITE_INDEX |
0 |
C_CTRL_PHYIF_RAS_N_INDEX |
0 |
C_CTRL_PHYIF_CAS_N_INDEX |
0 |
C_CTRL_PHYIF_WE_N_INDEX |
0 |
C_CTRL_RMW_INDEX |
0 |
C_CTRL_SKIP_0_INDEX |
0 |
C_CTRL_PHYIF_DQS_O_INDEX |
0 |
C_CTRL_SKIP_1_INDEX |
0 |
C_CTRL_DP_RDFIFO_PUSH_INDEX |
0 |
C_CTRL_SKIP_2_INDEX |
0 |
C_CTRL_AP_COL_CNT_LOAD_INDEX |
0 |
C_CTRL_AP_COL_CNT_ENABLE_INDEX |
0 |
C_CTRL_AP_PRECHARGE_ADDR10_INDEX |
0 |
C_CTRL_AP_ROW_COL_SEL_INDEX |
0 |
C_CTRL_PHYIF_FORCE_DM_INDEX |
0 |
C_CTRL_REPEAT4_INDEX |
0 |
C_CTRL_DFI_RAS_N_0_INDEX |
0 |
C_CTRL_DFI_CAS_N_0_INDEX |
0 |
C_CTRL_DFI_WE_N_0_INDEX |
0 |
C_CTRL_DFI_RAS_N_1_INDEX |
0 |
C_CTRL_DFI_CAS_N_1_INDEX |
0 |
C_CTRL_DFI_WE_N_1_INDEX |
0 |
C_CTRL_DP_WRFIFO_POP_INDEX |
0 |
C_CTRL_DFI_WRDATA_EN_INDEX |
0 |
C_CTRL_DFI_RDDATA_EN_INDEX |
0 |
C_CTRL_AP_OTF_ADDR12_INDEX |
0 |
C_CTRL_ARB_RDMODWR_DELAY |
0 |
C_CTRL_AP_COL_DELAY |
0 |
C_CTRL_AP_PI_ADDR_CE_DELAY |
0 |
C_CTRL_AP_PORT_SELECT_DELAY |
0 |
C_CTRL_AP_PIPELINE1_CE_DELAY |
0 |
C_CTRL_DP_LOAD_RDWDADDR_DELAY |
0 |
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY |
0 |
C_CTRL_DP_SIZE_DELAY |
0 |
C_CTRL_DP_WRFIFO_WHICHPORT_DELAY |
0 |
C_CTRL_PHYIF_DUMMYREADSTART_DELAY |
0 |
C_CTRL_Q0_DELAY |
0 |
C_CTRL_Q1_DELAY |
0 |
C_CTRL_Q2_DELAY |
0 |
C_CTRL_Q3_DELAY |
0 |
C_CTRL_Q4_DELAY |
0 |
C_CTRL_Q5_DELAY |
0 |
C_CTRL_Q6_DELAY |
0 |
C_CTRL_Q7_DELAY |
0 |
C_CTRL_Q8_DELAY |
0 |
C_CTRL_Q9_DELAY |
0 |
C_CTRL_Q10_DELAY |
0 |
C_CTRL_Q11_DELAY |
0 |
C_CTRL_Q12_DELAY |
0 |
C_CTRL_Q13_DELAY |
0 |
C_CTRL_Q14_DELAY |
0 |
C_CTRL_Q15_DELAY |
0 |
C_CTRL_Q16_DELAY |
0 |
C_CTRL_Q17_DELAY |
0 |
C_CTRL_Q18_DELAY |
0 |
C_CTRL_Q19_DELAY |
0 |
C_CTRL_Q20_DELAY |
0 |
C_CTRL_Q21_DELAY |
0 |
C_CTRL_Q22_DELAY |
0 |
C_CTRL_Q23_DELAY |
0 |
C_CTRL_Q24_DELAY |
0 |
C_CTRL_Q25_DELAY |
0 |
C_CTRL_Q26_DELAY |
0 |
C_CTRL_Q27_DELAY |
0 |
C_CTRL_Q28_DELAY |
0 |
C_CTRL_Q29_DELAY |
0 |
C_CTRL_Q30_DELAY |
0 |
C_CTRL_Q31_DELAY |
0 |
C_CTRL_Q32_DELAY |
0 |
C_CTRL_Q33_DELAY |
0 |
C_CTRL_Q34_DELAY |
0 |
C_CTRL_Q35_DELAY |
0 |
C_SKIP_1_VALUE |
15 |
C_SKIP_2_VALUE |
15 |
C_SKIP_3_VALUE |
15 |
C_SKIP_4_VALUE |
20 |
C_SKIP_5_VALUE |
36 |
C_SKIP_6_VALUE |
20 |
C_SKIP_7_VALUE |
36 |
C_B16_REPEAT_CNT |
0 |
C_B32_REPEAT_CNT |
0 |
C_B64_REPEAT_CNT |
0 |
C_BASEADDR_CTRL0 |
0x000 |
C_HIGHADDR_CTRL0 |
0x00d |
C_BASEADDR_CTRL1 |
0x00e |
C_HIGHADDR_CTRL1 |
0x017 |
C_BASEADDR_CTRL2 |
0x018 |
C_HIGHADDR_CTRL2 |
0x025 |
C_BASEADDR_CTRL3 |
0x026 |
C_HIGHADDR_CTRL3 |
0x02f |
C_BASEADDR_CTRL4 |
0x030 |
C_HIGHADDR_CTRL4 |
0x03d |
C_BASEADDR_CTRL5 |
0x03e |
C_HIGHADDR_CTRL5 |
0x047 |
C_BASEADDR_CTRL6 |
0x048 |
C_HIGHADDR_CTRL6 |
0x05b |
C_BASEADDR_CTRL7 |
0x05c |
C_HIGHADDR_CTRL7 |
0x06a |
C_BASEADDR_CTRL8 |
0x06b |
C_HIGHADDR_CTRL8 |
0x086 |
C_BASEADDR_CTRL9 |
0x087 |
C_HIGHADDR_CTRL9 |
0x09d |
C_BASEADDR_CTRL10 |
0x09e |
C_HIGHADDR_CTRL10 |
0x0a5 |
C_BASEADDR_CTRL11 |
0x0a6 |
C_HIGHADDR_CTRL11 |
0x0ad |
C_BASEADDR_CTRL12 |
0x0ae |
C_HIGHADDR_CTRL12 |
0x0b5 |
C_BASEADDR_CTRL13 |
0x0b6 |
C_HIGHADDR_CTRL13 |
0x0bd |
C_BASEADDR_CTRL14 |
0x0be |
C_HIGHADDR_CTRL14 |
0x0d0 |
C_BASEADDR_CTRL15 |
0x0d1 |
C_HIGHADDR_CTRL15 |
0x0d8 |
C_CTRL_BRAM_INIT_3F |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3E |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3D |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3C |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3B |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3A |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_39 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_38 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_37 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_36 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_35 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_34 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_33 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_32 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_31 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_30 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2F |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2E |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2D |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2C |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2B |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2A |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_29 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_28 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_27 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_26 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_25 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_24 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_23 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_22 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_21 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_20 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1F |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1E |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1D |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1C |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1B |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1A |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_19 |
0x000002FC000002FC000002FC000002FC000002FD000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_18 |
0x000002FC000002FC000002FC000002FC000002FC000002F0000002FC000002FC |
C_CTRL_BRAM_INIT_17 |
0x000002FC000042E8000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_16 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_15 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_14 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_13 |
0x000002FC000002FC000002FC000002FC000002FC000042E8000006FC000026F5 |
C_CTRL_BRAM_INIT_12 |
0x000006FC000026F4000006FC000026F4000006FC000026F4000006FC000026F4 |
C_CTRL_BRAM_INIT_11 |
0x000006FC000026F4000006FC000026F4000006FC000016F4000082FC000082FC |
C_CTRL_BRAM_INIT_10 |
0x000082F8000002FC000002FC000002FC000042E8000002FC000002FD000002FC |
C_CTRL_BRAM_INIT_0F |
0x000002FC000002FC0000093C000029240000093C000029240000093C00002924 |
C_CTRL_BRAM_INIT_0E |
0x0000093C000029240000093C000029240000093C000029240000093C00002924 |
C_CTRL_BRAM_INIT_0D |
0x0000093C000019240000803C000082FC000082F8000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_0C |
0x000042E8000006FC000026F5000006FC000026F4000006FC000026F4000006FC |
C_CTRL_BRAM_INIT_0B |
0x000016F4000082FC000082FC000082F8000002FC000002FC000002FC000042E8 |
C_CTRL_BRAM_INIT_0A |
0x000002FC000002FD000002FC000002FC000002FC0000093C000029240000093C |
C_CTRL_BRAM_INIT_09 |
0x000029240000093C000029240000093C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_08 |
0x000002FC000002FC000002FC000042E8000002FC000006FD000016F4000082FC |
C_CTRL_BRAM_INIT_07 |
0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD |
C_CTRL_BRAM_INIT_06 |
0x000002FC000002FC000002FC0000093C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_05 |
0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC |
C_CTRL_BRAM_INIT_04 |
0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD |
C_CTRL_BRAM_INIT_03 |
0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_02 |
0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC |
C_CTRL_BRAM_INIT_01 |
0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD |
C_CTRL_BRAM_INIT_00 |
0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_SRVAL |
0x0000002FC |
C_CTRL_BRAM_INITP_07 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_06 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_05 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_04 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_03 |
0x0000000000000000000000000000000000000000000000001111111111111111 |
C_CTRL_BRAM_INITP_02 |
0x1110000000000000000000000000000000011111111111111111111111111111 |
C_CTRL_BRAM_INITP_01 |
0x1110000000000000000011111111111111111111111111000000000111111011 |
C_CTRL_BRAM_INITP_00 |
0x1111111111110001111110111111111111111001111110111111111111111001 |
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